سال انتشار: ۱۳۸۴
محل انتشار: یازدهمین کنفرانس سالانه انجمن کامپیوتر ایران
تعداد صفحات: ۸
F. Safaei – Institute for Studies in Theoretical Physics and Mathematics (IPM
A. Khonsari – Dept. of Electrical and Computer Eng., Univ. of Tehran, Tehran, Iran.
M. Fathy – Dept. of Computer Eng.,Iran Univ. of Science and Technology, Tehran, Iran.
M. Ould-Khaoua – Dept. of Computing Science, University of Glasgow, UK.
One of the most important issues in the design of massively parallel systems is the development of efficient routing algorithms that provide high throughput and low latency in communications. These massively parallel systems are often composed of hundreds or thousands of components (such as routers, channels and connectors) that collectively possess failure rates higher than what arise in the ordinary systems. Therefore, these systems are required to be equipped with faulttolerant routings to ensure that the system will keep running in a degraded mode until the failed component is repaired. In this paper, we propose a new analytical model to capture the effects of faulty components in networks and to predict message latency in 2-dimensional torus with faults using Pipelined Circuit Switching (PCS) which is a popular routing and widely used in the literature for achieving fault-tolerance capability in networks. Simulation experiments reveal that the latency results predicted by the analytical model are in good agreement with those provided by the simulation model.