سال انتشار: ۱۳۸۴
محل انتشار: یازدهمین کنفرانس سالانه انجمن کامپیوتر ایران
تعداد صفحات: ۴
H. Parandeh-Afshar – University of Tehran School of Electrical and Computer Engineering
S.M Fakhraie – University of Tehran School of Electrical and Computer Engineering
In an attempt to improve the speed of VLSI signal processing systems, a new architecture for a high-speed Multiply- Accumulate (MAC) unit optimized for digital audio filters is proposed. This unit is designed as a coprocessor for the LEON RISC processor . In this work, four parallel MAC units with two coefficient register files and one values register file and a control unit are included in the coprocessor block. With the existence of parallel units, several SIMD-format instructions have been added to LEON instruction set. Each MAC unit has two 16-bit inputs, an internal 32-bit register and a programmable Round-Saturate block. The MAC unit uses a new architecture which embeds the accumulate part within the partial products summation tree of the multiplier with minimum overhead. A central control unit controls inputs of the four MACs and loading of registers. Experimental results show a high performance for digital audio filters.