سال انتشار: ۱۳۸۷

محل انتشار: دومین کنگره بین المللی علوم و فناوری نانو

تعداد صفحات: ۲

نویسنده(ها):

F Hasani – Nanoelectronic centre of excellence, VLSI laboratory, School of ECE, Tehran University, Tehran
N Masoumi –
M Fathipour – Nanoelectronic centre of excellence, Device laboratory, School of ECE, Tehran University, Tehran

چکیده:

With scaling down of technology feature sizes to nano scale dimensions, the interconnect resistance and coupling capacitance plays an important role in determining the delay and coupling effects of the circuit [1]. Coupling effects can cause interference between signals, referred to as crosstalk and may increase or decrease signal delay and as a result decrease signal integrity [2-3]. To analyze the coupling effects we need to model interconnects which require complete information of physical characteristic of the nets like the length of overlap or spacing between the nets [4]. The noise can also cause delay failure due to its effects on timing, increase power consumption due to glitches and change the logic level which cause functional failure [5]. The common methods used to reduce nano scale effects are driver sizing, buffer sizing, buffer insertion, wire sizing, wire spacing and shielding. Among these, driver sizing, buffer sizing, buffer insertion and shielding are difficult to be applied to post rout stage. In this work, we focus on interconnect delay, crosstalk noise and power optimization using wire sizing and wire spacing [6]. Critical factors in determining the magnitude of coupling voltage and delay include the victim’s wire length, victim’s wire width and its adjacency to the aggressor wire length. As the wire size of the net increases the interconnect delay decreases and the coupling capacitance increases. Wire spacing also changes the coupling capacitance. This simply shows that interconnect delay and crosstalk noise within a circuit are conflicting in nature. The proposed cost function can effectively meet performance specifications while minimizing crosstalk noise, delay and power according to their importance factor. Through this way each element of system is satisfied while the overall goals are reached