سال انتشار: ۱۳۹۱
محل انتشار: چهارمین کنفرانس مهندسی برق و الکترونیک ایران
تعداد صفحات: ۶
Mohsen jafari – School of Electrical and Computer EngineeringUniversity of TehranTehran, Iran
Mohsen Imani – School of Electrical and Computer EngineeringUniversity of TehranTehran, Iran
Morteza Fathipour – School of Electrical and Computer EngineeringUniversity of TehranTehran, Iran
this paper describes the design of a low power sampleand hold, implemented in 180-nm technology. Low noise andhigh performance sample and hold of the analog signals areallowed by the switch capacitor based circuit and an advancedtwo stage OTA. The circuit has 89dB signal to noise ratio (SNR)in Typical-Typical corner using ideal switches and improved fullydifferential two stages OTA. The proposed OTA provides936MHz unity-gain bandwidth,85dBgain, 60degree phasemargin and a differential peak to peak output swing more than2V. The total current of the above sample and hold circuit is4.2mA in typical corner. It was tested with supply voltagesbetween 1.8V and 1.65V and between -40 C and +120 C in allprocess corners. One of the main features of the proposedS&H(Sample & Hold) circuit is its small power dissipation whichresults from the low-power OTA configuration.Test andsimulation is done with HSPICE2008 tool and awanwaves forwave generation.