سال انتشار: ۱۳۹۰

محل انتشار: اولین همایش منطقه ای رویکردهای نوین در مهندسی کامپیوتر و فناوری اطلاعات

تعداد صفحات: ۴

نویسنده(ها):

Soheil Ziabakhsh – Department of Electrical Engineering, Roudsar and Amlash Branch, Islamic Azad University, Roudsar, Iran
Hosein Alavi-Rad – Departments of Electrical Engineering, Langaroud Branch, Islamic Azad University, Langaroud, Iran
Hasti Pourjafar – Departments of Mathematics, Islamic Azad University-Lahijan Branch, Lahijan, Iran
Saman Ziabakhsh – Department of Electrical Engineering, Lahijan Branch, Islamic Azad University, Lahijan, Iran

چکیده:

In this paper a new high speed 1-bit fast full adder cell with the least chip area and using the GDI technique is proposed. Simulation results performed by HSPICE in 0.35 μm CMOS process illustrate the superiority of the resulting proposed adder cell against several conventional CMOS 1-bit full adder cells in terms of gate area, delay, power dissipation, and PDP. Simulation results show that the proposed adder has the least propagation delay of 151.65 psec and power dissipation of 5.58 μW in a supply voltage of 2.8 V.