سال انتشار: ۱۳۹۱

محل انتشار: بیستمین کنفرانس مهندسی برق ایران

تعداد صفحات: ۴

نویسنده(ها):

Saleh Masoodian – Ferdowsi University of Mashhad, Mashhad, Iran
Mohsen A. Khalatbari –

چکیده:

In this paper a new control logic circuit for successive approximation register analog-to-digital converter (SA-ADC) is proposed. In the proposed digital circuit architecture, thenumber of flip-flops is reduced and the flip-flops do not need set and reset nodes. The simulation results of a 5-bit, 100 MS/s ADCin a 0.18-μm technology show that the digital power consumption of the proposed structure is reduced by a factor of 17% and the overall power consumption is reduced around 10% incomparison with the conventional counterpart.