سال انتشار: ۱۳۹۱
محل انتشار: دومین کنفرانس ملی مهندسی نرم افزار
تعداد صفحات: ۴
Hani JavanHemmat – Islamic Azad University, Lahijan Branch
Nima Karimpour Darav – Islamic Azad University, Lahijan Branch
The design of adders as the main parts of processors is a key issue in designing embedded processors. Because the adders being implemented must not only be fast but also lowpower. In this paper, we propose a new design of adders that exploits 1-out-of-n codes. In order to generate sum and carry signals, two circuits at switch level are presented.We demonstrate that both the circuits has no glitches (as the undesired activitiesof nodes) on their output. Moreover, only two switches havetransition on their states when inputs are changed. These two features guarantee that the activities of nodes related directly todynamic parameter of power dissipation stay as low as possible. Our evaluation based on simulation shows that the proposed adder has lower signal activities than a conventional adder, and we gain more reduction in the activities of nodes for bigger adders.