سال انتشار: ۱۳۹۱

محل انتشار: بیستمین کنفرانس مهندسی برق ایران

تعداد صفحات: ۵

نویسنده(ها):

Saman Kaedi – Department of Electrical and Computer Engineering Chamran University of Technology, Ahvaz, Iran
Ebrahim Farshidi – Department of Electrical and Computer Engineering Chamran University of Technology, Ahvaz, Iran

چکیده:

In this paper a new CMOS current-mode multiplier based on squarer circuit is proposed. The dual translinear loop is the basic building block in realizationscheme. Supply voltage is 1.8 V. The major advantages of this multiplier are low voltage, high speed, low power, immunity of body effect, high linearity and less dc offseterror. The circuit is designed and simulated using HSPICE simulator by level 49 parameters in 0.18μm CMOStechnology. The simulation results of analog multiplier demonstrate a THD of 1.24% in 1MHz, a −۳dB bandwidth of 31.2MHz and power consumption is less than 207 μW