دانلود مقاله A New Low Power-Delay-Product, Low-area, Parallel Prefix Adder With Reduction of Graph Energy
سال انتشار: ۱۳۹۰
محل انتشار: نوزدهمین کنفرانس مهندسی برق ایران
تعداد صفحات: ۶
M. Moghaddam – Dept. of Electrical Engineering Shahed University Tehran – IRAN
M. B. Ghaznavi-Ghoushchi –
In this paper the graph energy and electrical power consumption of various parallel prefix adders (PPA) are measured and investigated. By comparison the graph energy of PPAs with their power consumption, a linear relation between them is considered. Moreover, the measurements represent direct relation between arcs number and graph energy in PPA structures. Using these results a new PPA (proposed І) is introduced that it is achieved from Sklansky adder with reduction of graph energy and limiting the recursive stages to maximum 8 steps. A new standard, product of arc numbers and logic depth, is applied to compare the performance of proposed adder І with other PPAs. In addition using even and odd cells in proposed adder І resulted in proposed adder ІІ. All the simulations are done with Hspice and CMOS technology 180nm. Simulation results represent that power-delay-product of our 32-bit proposed adder І and ІІ come with about 17% and 35% improvement compared with Sklansky adder, respectively.