سال انتشار: ۱۳۹۰

محل انتشار: پنجمین کنفرانس بین المللی پیشرفتهای علوم و تکنولوژی

تعداد صفحات: ۸

نویسنده(ها):

Abdalhossein Rezai – Semnan University
Parviz Keshavarzi –
Reza Mahdiye –

چکیده:

This paper presents a new architecture for efficient implementation of neural network in hybrid CMOS/Nano hardware system. In this new architecture, latching switches are used in order to determine synaptic weights and each synaptic weight is implemented by just one latching switch. Using this new architecture, not only the CrossNet can be trained dynamically but also the number of CMOS transistors is decreased significantly. The results show that the proposed architecture leads to the higher speed, lower power consumption, and higher tolerance in the network compared to similar networks using other architectures. Therefore, the proposed structure has a huge potential to become an efficient implementation of neuromorphic networks based on nanodevice. In addition, the best results were achieved by implementing the proposed architecture in MLP networks